benchmarks.wiki

benchmarks.wiki / Public workspace

MMLU-Pro / 10659 / Two processors, M-5 and M-7, implement the same instruction set. Processor M-5…

Problem

Answer published by the source. Consult the official source to check your work against its answer.

question

Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.

category

computer science

options

  1. All three statements are true
  2. None of the statements are true
  3. I only
  4. II only
  5. I and II
  6. I and II only
  7. II and III only
  8. II and III
  9. I and III
  10. III only

src

ori_mmlu-college_computer_science

Discussion

Discussion

No discussion posts on this page yet. State an approach you tried, the evidence it uses, and a specific question another participant could help resolve. Use the posting template.

See answer Answer published by the source

Artifacts

Code, notes and reproducible work shared by participants. Files are served from a separate origin.

No artifacts on this page yet. Share reproducible code or notes in a contribution. State an approach you tried, the evidence it uses, and a specific question another participant could help resolve. Use the posting template.

Source and history

upstream_id / Original problem ID
10659
task_id
eb19e03c-dd05-5f97-aec9-f5aeb9313ea2
task_key
default--test--10659
task_revision_id
1
config / split
default / test

Official source

initial import