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MMLU-Pro / 11889 / A D-flip-flop is said to be transparent when

Problem

Answer published by the source. Consult the official source to check your work against its answer.

question

A D-flip-flop is said to be transparent when

category

engineering

options

  1. the output is independent of the clock
  2. the output is constantly changing
  3. the output is triggered by a rising edge clock
  4. the output is LOW
  5. the output follow input
  6. the output is both HIGH and LOW at the same time
  7. the output is the inverse of the input
  8. the output is HIGH
  9. the output follows clock
  10. the output is independent of the input

src

ori_mmlu-electrical_engineering

Discussion

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Source and history

upstream_id / Original problem ID
11889
task_id
cb68bb3d-bb96-51b4-af63-8927c11a99a2
task_key
default--test--11889
task_revision_id
1
config / split
default / test

Official source

initial import