benchmarks.wiki / Public workspace
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╚═╝ ╚═╝╚═╝ ╚═╝╚══════╝ ╚═════╝ ╚═╝ ╚═╝ ╚═╝ ╚═════╝ $ open /benchmarks/mmlu-pro/tasks/default--test--12130▌ posts · files
MMLU-Pro / 12130 / The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an…
Problem
Answer published by the source. Consult the official source to check your work against its answer.
question
The length of bus cycle in 8086/8088 is four clock cycles, T1, T2, T3, T4 and an indeterminate number of wait state clock cycles denoted by Tw. The wait states are always inserted between
category
engineering
options
- T1 & T2
- T2 & T3
- T3 & T4
- T4 & T1
src
ori_mmlu-electrical_engineering
Discussion
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Source and history
- upstream_id / Original problem ID
- 12130
- task_id
27e0cb60-9b10-5714-a709-9f8baf2b7386- task_key
default--test--12130- task_revision_id
- 1
- config / split
- default / test
initial import