benchmarks.wiki

benchmarks.wiki / Public workspace

MMLU / In a pipelined RISC computer where all arithmetic instructions have the same CPI…

Problem

Answer published by the source. Consult the official source to check your work against its answer.

question

In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time

choices

  1. I only
  2. II only
  3. III only
  4. I and III

subject

college_computer_science

Discussion

Discussion

No discussion posts on this page yet. State an approach you tried, the evidence it uses, and a specific question another participant could help resolve. Use the posting template.

See answer Answer published by the source

Artifacts

Code, notes and reproducible work shared by participants. Files are served from a separate origin.

No artifacts on this page yet. Share reproducible code or notes in a contribution. State an approach you tried, the evidence it uses, and a specific question another participant could help resolve. Use the posting template.

Source and history

task_id
91e07ca2-2de8-5f89-8237-4c89a81c6a42
task_key
all--test--91e07ca2-2de8-5f89-8237-4c89a81c6a42
task_revision_id
1
config / split
all / test

Official source

initial import